1. Field of the Invention
This invention relates to clock and data recovery circuits and, more particularly, to techniques for clock and data recovery.
2. Description of the Related Art
High-speed data communication systems frequently rely on clock and data recovery (CDR) circuits within the receiver instead of transmitting a reference clock with the data. The CDR extracts a clock that is embedded in the incoming data stream. Once a clock is recovered, it is used to sample the incoming data stream to recover the individual bits. A variety of clock recovery circuits are well known, including phase-locked loops (both analog and digital) and delay lock loops. Regardless of the circuit used, a clock recovery circuit attempts to extract the frequency and phase of the clock from a data stream.
During propagation, data signals may experience distortion due to bandwidth limitations, dispersion, etc. in the communication channel. These effects cause a spreading of signal pulse energy from one symbol period to another. The resulting distortion is known as inter-symbol interference (ISI). Generally speaking, ISI becomes worse as the speed of communication increases. As a result, high-speed communication systems often incorporate circuitry to equalize the effects of ISI. One technique for reducing the effect of ISI is to use an adaptive equalizer such as a decision feedback equalizer (DFE).
DFE's produce an equalized data stream as follows. A clock recovered from the data is used to sample the data at regular intervals. The output of the sampler, which constitutes the retimed data, is stored in a series of latches. The input of the sampler includes the original data plus the individually weighted outputs from each latch. The weights are determined adaptively by analyzing the resulting data stream. Over time, the DFE is expected to produce a stable set of weights that equalize ISI. In order to function properly, the DFE requires a stable recovered clock.
To recover a stable clock, one type of CDR uses an algorithm known as the Muller-Mueller algorithm. One aspect of the Muller-Mueller algorithm is that it uses only one sample per symbol of the received data to determine the timing error between the extracted clock and transitions of the received data. Performance of the Muller-Mueller algorithm is improved if the received signal is equalized before being sampled. However, as previously noted, a DFE requires a stable clock in order to perform equalization. Hence, these DFE-based CDR systems include two interdependent adaptation loops. This interdependence can cause difficulty in startup situations both the CDR and DFE are initializing. Convergence of clock timing and DFE adaptation may take an excessively long time, or may never occur. Previous attempts to improve convergence involve complex systems to limit the range of DFE weights or to predict the proper weights via sophisticated modeling of the expected ISI. Alternatively, a clock training pattern is sometimes transmitted while the DFE coefficients are held fixed, allowing the CDR to adapt first. Once the CDR is stable, the DFE coefficients are permitted to vary, in the hope that stable coefficients will be found within a reasonable time. Unfortunately, these methods are often insufficient to reduce convergence times to acceptable levels. What is needed are systems and methods of rapidly and efficiently initializing adaptive, interdependent DFE and CDR loops.